留学主题咨询
美国EECS TOP50项目全方位咨询
其他 计算机 选校 暑研 TOP50 电子- 课程简述: 从当前科研实习背景的深度挖掘分析，暑研套磁及申请，未来背景提升方向规划，到美国所有TOP50 EECS项目的档次划分，各项目优劣势分析。针对个人进行与项目匹配度的针对性测试，最终敲定选校list以及后期的提升方向（包含8-12所学校）。
- 适用用户: 美国EECS方向TOP50研究生申请者
自我介绍
自我介绍
我凭借丰富的科研背景以及优秀的文书写作，以并不出众的本科背景获得了Caltech MSEE，UCLA MSECE UPenn MSEE 等名校offer。
除此以外，我还为多名学生进行留学咨询，辅导的同学获得了包括 Stanford EE, Caltech EE, CMU ECE, Princeton ECE，Harvard DS等世界顶尖项目的offer。
希望能为背景不出众的每一位同学找到属于自己的申请道路。
我相信没有背景不好的学生，只有不会挖掘学生背景的老师。留学申请不仅是学生将自己呈现给学校的过程，也是导师帮助学生不断了解自己的过程，力求让学生在申请的现有条件下达到最优解。
教育经历
教育
教育
University of California, Los Angeles
Master Electrical and Computer Engineering
经历
经历
FPGA Engineer
Suzhou Keda Technology Software Research & Development Center
• Conducted timing analysis of I2C and I2S protocols and wrote protocol-based communication programs
• Carried out simulation test of the I2C programs by adopting modelsim
• Accomplished the whole procedure of the VLSI design
Mixed Signal IC Designer
Mixed Signal IC Design Research Group in the Institute of Microelectronics
• Experience the whole procedure of the design and fabrication of the Analog-to-Digital Converter: circuit design, optimization of speed and energy, post-simulation, tape-out, testing and encapsulation
• Learn the standard parameter in IC design and the basic circuit topology optimization of analog integrated circuits
• Complete the circuit design of the mix-structured pipelined-SAR ADC
• Study the rapid-converging digital calibration technology of high-powered converter
• Ease the design constraints of high-powered ADC from many aspects, e.g., structure, property, area and power consumption
Research assistant
Advanced Semiconductor Device & Optoelectronics Integration Laboratory
• Serve as the research assistant of Prof. Luo and do frontier research of micro-nano devices based on lowdimensional semiconductor nanostructures
• Do characterization and fabrication of the MAPbI3 perovskite/Si heterojunction photodetector arrays for image sensing application
• Conduct fabrication and structural simulation of the Graphene/GaAs and Ga2O3/GaAs integrated photodetector devices
Research assistant
Digital Integrated Circuits Research Group in UCLA
• Mastered static and dynamic properties of digital logic and studied CMOS scaling and energy components
• Learned the principles in building digital logic in static CMOS and PTL, gate sizing and its application
• Used the design expertise acquired in group to design the algorithm, determine the circuit topology and choose logic style that best optimizes the delay-energy metric of the Absolute-value Detector
• Identified input vectors that will exercise critical path, sized the gates for minimum delay and did VDD scaling
• Composed a paper related to the comparator’s offset based on the above study and published it as the first and corresponding author
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